Course Glossary

A B C D E F G H I L M N O P R S T U V W Y

A

• Activation. The move of dopant atoms onto lattice sites, where they supply carriers (Module 6)
• Anisotropic. Proceeding faster in one direction, usually straight down (Module 7)
• Annealing. Heating the wafer to repair damage and activate dopants (Module 6)
• Atomic layer deposition. Deposition one atomic layer per cycle by two self-limiting reactions (Module 8)
• Atomic layer etching. Etching that removes one atomic layer per cycle (Module 7)

B

• Band gap. The energy an electron needs to move from the valence band to the conduction band (Module 1)
• Barrier layer. A thin liner that stops copper from spreading into nearby materials (Module 9)
• Bottom-up synthesis. Building a structure by joining designed molecules (Module 11)

C

• Carbon nanotube. A cylinder of carbon atoms about a nanometer across (Module 11)
• Carrier. A mobile charge that carries current, either an electron or a hole (Module 1)
• Channel. The thin conducting layer under the gate that joins source and drain when the transistor is on (Module 1)
• Channeling. The deep travel of ions along open rows in the crystal (Module 6)
• Chemical vapor deposition. Deposition by a chemical reaction of gases on the wafer surface (Module 8)
• Chemical-mechanical polishing. Polishing that combines a chemical reaction with fine abrasion to give a flat, smooth surface (Module 2)
• Chiplet. A small chip designed to be combined with others in one package (Module 9)
• Cleanroom. A room in which the number of airborne particles is controlled to a stated limit (Module 3)
• CMOS. Complementary MOS, a circuit style that pairs n-channel and p-channel transistors (Module 1)
• Compound semiconductor. A semiconductor made of two or more elements, such as gallium arsenide (Module 11)
• Conformal film. A film with the same thickness on every surface (Module 8)
• Critical dimension. The width of the smallest feature in a layer, such as the gate line (Module 10)
• Crystal orientation. The crystal plane that lies along the wafer surface, such as (100) (Module 2)
• Czochralski method. Growing a single crystal by pulling a seed slowly out of molten silicon (Module 2)

D

• Damascene process. Making wires by etching trenches, filling them with metal, and polishing (Module 9)
• Defect density. The average number of fatal defects per unit area of wafer (Module 3)
• Deionized water. Water purified until almost no dissolved ions remain (Module 3)
• Developer. The solution that dissolves the soluble part of the resist after exposure (Module 4)
• Dielectric constant. A measure of how much an insulator increases capacitance, written k (Module 5)
• Diffraction. The bending of light at edges, which blurs small features (Module 4)
• Diffusion. The movement of atoms from regions of high concentration to regions of low concentration (Module 6)
• Doping. Adding a small, controlled amount of another element to change the carrier concentration (Module 1)
• Dose. The number of implanted ions per square centimeter (Module 6)
• Dry oxidation. Oxidation in oxygen, slow and of the highest quality (Module 5)

E

• Electromigration. The slow movement of metal atoms in a wire caused by a high current (Module 9)
• Electroplating. Depositing metal from a solution with an electric current (Module 9)
• Endpoint. The moment an etch has cleared the film (Module 7)
• Epitaxy. Growth of a crystal film that continues the crystal of the wafer (Module 8)
• Equivalent oxide thickness. The thickness of silicon dioxide that would give the same capacitance (Module 5)
• Etch rate. The thickness of film removed per unit time (Module 7)
• EUV lithography. Lithography with 13.5 nm light, using mirrors in vacuum (Module 4)
• Evaporation. Deposition by boiling a material in vacuum (Module 8)

F

• Flip chip. Mounting a chip face down on solder bumps (Module 9)
• FOUP. Front opening unified pod, a sealed carrier that holds 25 wafers (Module 3)

G

• Gate. The terminal whose voltage turns the transistor on or off (Module 1)
• Gate insulator. The thin insulating layer between the gate and the channel (Module 5)
• Graphene. A single layer of carbon atoms in a honeycomb pattern (Module 11)
• Graphene nanoribbon. A strip of graphene a few atoms wide, with a band gap set by its width and edges (Module 11)

H

• HEPA filter. A high-efficiency air filter that removes 99.97% of particles 0.3 µm in size (Module 3)
• Heterogeneous integration. Combining different materials or chips into one system (Module 11)
• High-k dielectric. An insulator with a dielectric constant well above that of silicon dioxide (Module 5)
• Hole. An empty electron state in the valence band that behaves like a mobile positive charge (Module 1)

I

• Immersion lithography. Lithography with water between the lens and the wafer to raise the numerical aperture (Module 4)
• Ingot. The cylinder of single-crystal silicon produced by crystal growth (Module 2)
• Interconnect. The metal wiring that links the transistors on a chip (Module 9)
• Interface trap. A broken bond at the boundary between silicon and oxide that can catch carriers (Module 5)
• Ion implantation. Doping by firing charged dopant atoms into the wafer (Module 6)
• ISO class. A rating of cleanroom air based on the allowed number of particles per cubic meter (Module 3)
• Isotropic. Proceeding at the same rate in every direction (Module 7)

L

• Laminar flow. Air moving in smooth, parallel streams that carry particles away without mixing (Module 3)
• Lift-off. Patterning by depositing a film over resist and then dissolving the resist (Module 8)
• Low-k dielectric. An insulator with a dielectric constant below that of silicon dioxide (Module 9)

M

• Mask. A plate that carries the pattern for one layer, also called a reticle (Module 4)
• Mobility. A measure of how easily carriers move through a material in an electric field (Module 11)
• Molybdenum disulfide. A layered semiconductor whose single layer is three atoms thick (Module 11)
• MOSFET. Metal-oxide-semiconductor field-effect transistor, the switch used in nearly all chips (Module 1)
• Multiple patterning. Building one layer from two or more exposures or from deposited sidewall films (Module 4)

N

• n-type and p-type. Silicon doped so that electrons (n-type) or holes (p-type) are the majority carriers (Module 1)
• Native oxide. The very thin oxide that forms on silicon in air at room temperature (Module 3)
• Numerical aperture. A measure of how wide a cone of light a lens collects (Module 4)

O

• Overlay. How accurately a new pattern lines up with the patterns beneath it (Module 4)

P

• p-n junction. The boundary between p-type and n-type regions, which passes current in one direction (Module 1)
• Photoresist. A light-sensitive coating that becomes more or less soluble where it is exposed (Module 4)
• Physical vapor deposition. Deposition in which atoms travel from a solid source to the wafer (Module 8)
• Plasma. A gas in which some atoms or molecules have been ionized (Module 7)
• Plasma-enhanced CVD. CVD in which a plasma supplies energy so the wafer can stay cooler (Module 8)
• Polysilicon. Silicon made of many small crystals, either as purified feedstock or as a deposited film (Module 2)
• Positive and negative resist. Resists in which the exposed areas dissolve (positive) or remain (negative) (Module 4)
• Precursor. A gas or vapor that supplies an element for the film (Module 8)
• Process flow. The complete ordered list of steps used to make a chip (Module 10)
• Process integration. The work of combining individual steps into a flow that works as a whole (Module 10)
• Projected range. The average depth at which implanted ions come to rest (Module 6)

R

• Radical. A neutral, highly reactive fragment of a molecule (Module 7)
• RCA clean. The standard two-bath wet cleaning sequence for silicon wafers (Module 3)
• Reactive ion etching. Plasma etching that combines chemical reaction with ion impact (Module 7)
• Replacement metal gate. A process in which a temporary gate is removed and replaced with the final gate (Module 10)

S

• Scanner. A projection tool that exposes one field at a time and steps across the wafer (Module 4)
• Segregation coefficient. The ratio of an impurity’s concentration in the solid to that in the liquid during freezing (Module 2)
• Selectivity. The ratio of the etch rates of two materials in the same etch (Module 7)
• Self-alignment. Using a structure already on the wafer as the mask for the next step (Module 10)
• Shallow trench isolation. Oxide-filled trenches that separate neighboring transistors (Module 10)
• Sheet resistance. The resistance of a thin layer, in ohms per square (Module 6)
• Silica. Silicon dioxide, the form in which silicon occurs in quartz sand (Module 2)
• Silicide. A compound of a metal with silicon that gives a low-resistance contact (Module 9)
• Single crystal. A solid in which the atomic pattern continues unbroken through the whole piece (Module 2)
• Spacer. A thin wall of insulator left on the side of the gate (Module 10)
• Sputtering. Deposition by knocking atoms from a target with ions (Module 8)
• Statistical process control. Tracking measurements over time to catch a process that is drifting (Module 10)
• Step coverage. The ratio of film thickness on a sidewall to that on the top surface (Module 8)
• Strained silicon. Silicon whose atoms are slightly stretched or compressed to speed up carriers (Module 10)

T

• Thermal budget. The total amount of heat a wafer receives during processing (Module 6)
• Thermal oxidation. Growing silicon dioxide by heating silicon in oxygen or steam (Module 5)
• Threshold voltage. The gate voltage at which the channel forms (Module 1)
• Through-silicon via. A copper column that passes through a chip to connect stacked chips (Module 9)
• Tunneling. The quantum effect that lets electrons pass through a very thin insulator (Module 5)
• Two-dimensional material. A crystal that is stable as a single layer one or a few atoms thick (Module 11)

U

• Undercut. Removal of film beneath the edge of the mask (Module 7)

V

• Via. A vertical plug that connects one wiring layer to the next (Module 9)

W

• Wafer. A thin, polished slice of the ingot on which chips are built (Module 2)
• Well. A doped region that provides the right background for one type of transistor (Module 10)
• Wet oxidation. Oxidation in steam, fast and used for thick layers (Module 5)
• Wide-bandgap semiconductor. A semiconductor with a band gap well above that of silicon, such as silicon carbide or gallium nitride (Module 11)

Y

• Yield. The fraction of chips on a wafer that work (Module 3)

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