A Complete CMOS Process

In plain language

The earlier modules covered one kind of step at a time. A real chip is built by repeating those steps in a careful order. A layer is deposited, a pattern is printed, the layer is etched or the silicon is doped, the resist is stripped, the wafer is cleaned and measured, and the cycle begins again.

A leading-edge wafer passes through many hundreds of steps and spends about three months in the fab. The order matters. Each hot step moves the dopants that are already in place, each etch must stop on the right layer, and each pattern must line up with those beneath it.

Image

Figure 1. The main stages of a CMOS process. The front end builds the transistors and the back end wires them together.

Core lesson

Step 1. The starting wafer

The process begins with a polished p-type wafer with a (100) surface, as described in Module 2. It is cleaned and given a thin protective oxide.

Step 2. Isolation

Neighboring transistors must not affect each other. Shallow trenches are etched into the silicon around the area of each transistor, filled with deposited oxide, and polished flat. This is called shallow trench isolation.

Step 3. Wells

A CMOS chip needs both n-channel and p-channel transistors on the same wafer. An n-channel transistor must sit in p-type silicon and a p-channel transistor in n-type silicon. Two masked implants create these regions, called the p-well and the n-well, and an anneal activates them.

Step 4. The gate stack

The gate insulator is formed, and the gate material is deposited over it. The gate pattern is then printed and etched. This is the most demanding pattern in the whole process, because the width of the gate line sets the channel length of the transistor. The etch must cut through the gate material and stop on an insulator only a few atoms thick, which calls for very high selectivity.

Step 5. Source and drain

The source and the drain are implanted with the gate already in place. The gate blocks the ions, so the doped regions line up with the edges of the gate without any separate alignment. This idea is called self-alignment, and it is one of the most useful ideas in chip making, because it removes an alignment error that could not otherwise be avoided.

In practice the step has three parts. A shallow, light implant forms the regions next to the channel. A film is then deposited evenly over the gate and etched straight down, which leaves a thin wall of insulator, called a spacer, on each side of the gate. A heavier implant then forms the main source and drain regions a small distance from the channel. A rapid anneal activates the dopants. The n-channel and the p-channel transistors receive their implants separately, each with its own mask.

Step 6. Contacts

Silicide is formed on the source, the drain, and the gate. An insulator is deposited and polished, contact holes are etched down to the silicide, and the holes are filled with tungsten.

Step 7. Metal layers

The copper wiring is built layer by layer with the damascene process from Module 9. Each layer needs its own lithography, etching, deposition, plating, and polishing steps.

Step 8. Test and package

A final protective layer is added and opened over the pads. The chips are tested on the wafer, cut apart, packaged, and tested again.

What changed in modern processes

The flow above describes a classic flat transistor. Today’s processes keep the same logic and add to it. The gate that is patterned first is now a temporary stand-in. After the source and drain anneal, it is removed and replaced with a high-k insulator and a metal gate, which could not have survived that anneal. Silicon mixed with germanium is grown in the source and drain to strain the channel and speed up the carriers.

In a FinFET, thin vertical fins of silicon are etched first, and the gate wraps over them. In the newest transistors, alternating crystal layers are grown and etched into fins, and one of the two materials is then removed by a selective etch to leave thin sheets of silicon. ALD wraps the gate insulator and the gate metal around each sheet. Every one of these changes is built from the unit steps in this course.

Keeping the flow under control

Process integration engineers own the flow as a whole. They decide the order of steps and make sure each step leaves the wafer ready for the next. Film thickness, line width, and alignment are measured after critical steps. Small test structures between the chips are measured electrically. The results are tracked with statistical methods, so a tool that begins to drift is caught before it damages many wafers.

Going deeper

These sections add the equations behind the core lesson, each with a worked example. They assume first-year algebra and can be skipped without losing the thread of the course.