Semiconductor Fabrication: From Sand to Chip · Module 9
Interconnects and Packaging
Billions of transistors do nothing until they are wired together. This module covers the wiring above the transistors and the package around the chip.
What you will learn
- How transistors are connected to the wiring above them
- Why copper and low-k insulators replaced aluminum and silicon dioxide
- How the damascene process and polishing build each wiring layer
- How finished chips are tested, packaged, and stacked
In plain language
Above the transistors, a chip carries a stack of metal wiring layers separated by insulators. An advanced chip has more than ten of them. Vertical plugs called vias connect one layer to the next. The lowest wires are the thinnest and link neighboring transistors. The upper wires are thick and carry power and signals across the whole chip.
When the wafer is finished, every chip on it is tested. The wafer is cut into individual chips, and each good one is mounted in a package that protects it and connects it to a circuit board. Packaging has grown in importance, because placing several chips side by side or on top of each other in one package is now a main way to build more capable systems.
ANNLab, University of Arizona
Figure 1. A simplified cross-section of a chip. The wires grow thicker toward the top of the stack.
Core lesson
Front end and back end
Engineers divide the process into two parts. The front end builds the transistors in the silicon. The back end builds the wiring above them. The steps differ in one basic way. Front-end steps can run at 1,000 °C, while back-end steps must stay near or below 400 °C to protect the metal.
Making contact to the transistor
Metal placed directly on silicon often makes a poor electrical contact. A thin layer of silicide, a compound of a metal such as nickel or titanium with silicon, is therefore formed on the source, the drain, and the gate. An insulator is deposited over the transistors, holes are etched down to the silicide, and the holes are filled with tungsten.
Why wires limit speed
A signal on a wire is delayed by the resistance of the wire and by the capacitance between it and its neighbors. Thinner wires have more resistance, and closer wires have more capacitance. As transistors became faster, the wires became the slower part of the circuit.
The industry responded with two changes in materials. Copper replaced aluminum starting in the late 1990s, because copper has lower resistance and stands up better to high currents. Insulators with a lower dielectric constant than silicon dioxide, called low-k dielectrics, replaced the oxide between the wires to reduce capacitance.
The damascene process
Copper cannot be plasma etched in a practical way, so the wires are made by filling instead of cutting. The pattern is etched into the insulator as trenches for the wires and holes for the vias. A thin barrier layer is deposited to line them, because copper atoms move easily through insulators and would harm the transistors. A thin copper seed layer follows. The trenches are then filled with copper by electroplating, and the excess copper on top is polished away. One cycle forms one wiring layer and its vias, and the cycle repeats for each layer.
Chemical-mechanical polishing
In chemical-mechanical polishing, or CMP, the wafer is pressed face down on a rotating pad that is wet with a slurry. The slurry contains fine abrasive particles and chemicals that soften the surface. Together they remove the high spots and leave the wafer flat. Flatness matters because lithography keeps its image sharp only over a very small range of height, as Module 4 showed. Without CMP, a stack of ten wiring layers could not be printed.
Reliability
A wire that works on the first day must work for years. At high current density, the flow of electrons slowly pushes metal atoms along the wire. Empty spaces open up and can break the connection. This effect is called electromigration, and design rules limit the current in each wire to control it. Insulators can also break down slowly under voltage. Chips are tested under raised temperature and voltage to check that they will last.
Test and packaging
Fine needles touch the pads of each chip on the wafer to test it. The wafer is then cut with a saw or a laser. Each good chip is attached to a package base and connected either by thin bonding wires or by tiny solder bumps on its face, an arrangement called flip chip. A molded cover protects the chip, and the finished part is tested again.
Advanced packaging
Several chips can share one package. They may sit side by side on a silicon base with very fine wiring, or be stacked and connected by vertical copper columns that pass through the silicon. In the newest method, the copper pads of two chips are bonded directly to each other. Building a system from several smaller chips, often called chiplets, improves yield, since small chips have higher yield than large ones, as Module 3 showed. It also lets each part be made in the process that suits it best.
Going deeper
These sections add the equations behind the core lesson, each with a worked example. They assume first-year algebra and can be skipped without losing the thread of the course.
R = ρ L / (W H)
Here ρ is the resistivity of the metal, L the length of the wire, and W and H its width and height.
Worked example
A copper wire is 20 nm wide, 40 nm high, and 10 µm long. With the bulk resistivity of copper, 1.7 × 10−6 Ω·cm, the resistance is 1.7 × 10−6 × 10−3 / (8 × 10−12) = 210 Ω. The real value is several times higher. Electrons scatter from the surfaces and grain boundaries of such a narrow wire, and the barrier layer takes up part of the cross-section.
The delay of a wire is proportional to the product of its resistance and its capacitance. Both are proportional to the length, so the delay rises with the square of the length.
Worked example
Suppose the width, the height, and the spacing of a wire are all halved while its length stays the same. The cross-section falls to a quarter, so the resistance rises four times. The capacitance per unit length stays roughly the same, because the smaller height and the smaller spacing cancel. The delay rises four times. This is why long connections are routed on the thick upper layers.
The median time to failure of a wire is described by Black’s equation.
MTTF = A J−n eEa / kT
J is the current density, and the exponent n is close to 2 for many cases.
Worked example
With n = 2, doubling the current density in a wire cuts its expected lifetime to one quarter. Lifetime also falls quickly with temperature, which is why chips are stress-tested hot.
Check your understanding
Try each question before opening the answer. The last question uses the Going deeper material.
Copper has lower resistance, which reduces delay, and it resists electromigration better, so it can carry more current for longer.
Copper does not form a gas in a plasma etch at practical temperatures, so it cannot be etched cleanly. Trenches are etched in the insulator instead, filled with copper, and polished flat.
It stops copper atoms from moving into the insulator and down to the transistors, where they would cause failures.
It removes excess material and leaves the wafer flat. Lithography can focus only over a very small range of height, so each layer must be flat before the next pattern is printed.
The cross-section is 5 × 10−11 cm2 and the length is 10−2 cm. R = 1.7 × 10−6 × 10−2 / (5 × 10−11) = 340 Ω.
Key terms
- Interconnect. The metal wiring that links the transistors on a chip
- Via. A vertical plug that connects one wiring layer to the next
- Silicide. A compound of a metal with silicon that gives a low-resistance contact
- Low-k dielectric. An insulator with a dielectric constant below that of silicon dioxide
- Damascene process. Making wires by etching trenches, filling them with metal, and polishing
- Barrier layer. A thin liner that stops copper from spreading into nearby materials
- Electroplating. Depositing metal from a solution with an electric current
- Electromigration. The slow movement of metal atoms in a wire caused by a high current
- Flip chip. Mounting a chip face down on solder bumps
- Through-silicon via. A copper column that passes through a chip to connect stacked chips
- Chiplet. A small chip designed to be combined with others in one package
In the fab
Back-end engineers, polishing engineers, and reliability engineers work on the wiring. Packaging and test employ many engineers and technicians, and this part of the industry is expanding in the United States.
Further reading
J. D. Plummer and P. B. Griffin, Integrated Circuit Fabrication: Science and Technology, Cambridge University Press. The authors offer a prepublication version that is free to read on the Stanford book site (opens in a new tab).
Previous: Module 8Course homeNext: Module 10, A Complete CMOS Process
Created by Prof. Zafer Mutlu, ANNLab, University of Arizona.